AI Surge Makes Advanced Chip Packaging the Next Semiconductor Battleground
By Wen-Yee Lee
The Rise of Advanced Chip Packaging in the AI Era
TAIPEI, Nov 6 (Reuters) - A global race to build AI infrastructure is unleashing billions of dollars of investment in advanced chip packaging, a once unglamorous aspect of technology that has become a critical bottleneck in turning out the world's most powerful processors.
As demand for artificial intelligence chips outstrips available packaging capacity, companies from Nvidia and AMD to lesser-known players in Taiwan are expanding production, while equipment makers develop new tools, interviews with more than a dozen industry executives and analysts show.
The Changing Role of Packaging
"Packaging was always that thing that you just didn't worry about," former Intel chief executive Pat Gelsinger, now a partner at Playground Global, told reporters in Taipei recently.
Advanced packaging could eventually account for as much as half the value of a chip product, Gelsinger estimated, as some of today's graphics and central processing units can integrate 10 or more chips, sometimes as many as 20.
Revenue from advanced packaging is forecast to overtake that earned via the traditional route for the first time in 2026, says research firm Yole Group, with capital spending on the technology expected to near $28 billion.
TSMC's Dominance and Industry Response
Taiwan Firm Dominates Chip-on-Wafer Substrate
The world's largest contract chipmaker, Taiwan's TSMC, dominates the most sophisticated advanced packaging technology, including chip-on-wafer-on-substrate, or CoWoS.
The technology links separate pieces of silicon, such as processors and memory chips, on a shared base, to let them work together at high speed.
It is widely used by Nvidia, AMD and Broadcom, as well as cloud companies developing their own AI chips.
But TSMC's capacity limits have spurred some chip designers to seek additional supply.
Nvidia's Strategic Investments
Nvidia, for example, is providing billions of dollars in financing to expand CoWoS packaging capacity at Siliconware Precision Industries, or SPIL, a unit of Taiwan's ASE Technology, said an industry executive familiar with the matter, who sought anonymity for lack of authorisation to talk to media.
The funding will support new factory space and equipment, the executive said. The scale of the support has not previously been reported.
Nvidia did not respond to a request for comment. ASE said it does not comment on market rumours involving its customers.
A Fundamental Chipmaking Shift
The scramble to invest reflects a broader change in manufacturing of powerful chips, as more chip designers use advanced packaging to integrate multiple chips, such as processors and memory, into a single package.
That allows the ensemble to work together faster as one system, in contrast with the practice of decades, when packaging served mainly to protect chips and provide the electrical connections to attach them to circuit boards.
The shift comes as it become harder and costlier to win performance gains by shrinking and adding transistors, the tiny switches inside a chip.
The newer packaging technique is especially important for AI chips, which need to shuffle vast amounts of data between processors and nearby memory. Speeding up such transfers hastens the process of training and running AI models.
The Search for TSMC Alternatives
A Race for TSMC Alternatives
TSMC's tight capacity offers an opportunity for smaller suppliers, such as Taiwan's Powertech Technology.
"Everyone is looking for a solution outside TSMC," its chairman, D K Tsai, told reporters in August. "They don't want to rely entirely on TSMC."
Powertech, also known as PTI, is betting on panel-level packaging, which uses larger rectangular panels instead of round wafers as the chip packaging platform.
This way, it can accommodate more chips in each production run and waste less material, an advantage as AI processors become larger and more complex.
PTI is working with AMD and Broadcom on the technology as the industry seeks to demonstrate its viability for larger, more complex chip packages used in AI and high-performance computing.
"The most important thing right now is capacity," said PTI Senior Vice President Jim Lin, adding that customers were waiting for the company to ramp up production.
Powertech's Expansion and Industry Collaboration
Powertech plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore. Production could begin in 2028, Tsai said.
To support larger and more complex chip packages, TSMC is developing its own panel-based technology, called chip-on-panel-on-substrate, or CoPoS.
In April, it said it had built a pilot line and expected production to begin within a couple of years, but CoWoS remains TSMC's main AI-packaging technology.
AMD has also unveiled investments of more than $10 billion across Taiwan's semiconductor industry, including partnerships with ASE, SPIL and Powertech on advanced packaging.
Asked if Powertech's panel-level packaging technology could offer an alternative to TSMC's technology, AMD Chief Executive Lisa Su did not directly address the question but acknowledged the need for more advanced packaging capacity.
"I think CoWoS and advanced packaging are super important for our high-performance computing going forward," Su told Reuters in Taipei in October.
"TSMC has been an incredible partner in advanced packaging, and we're going to continue to do more together. And yes, we do need more capacity overall."
Panel-level packaging would reduce material waste when packaging larger AI chips, said Microsoft Azure hardware chief Rani Borkar, though the company has not decided whether or when it will adopt the technology.
Chip Equipment Makers Enter the Market
Chip Equipment Makers Join the Rush
The packaging boom is also opening a new market for makers of semiconductor equipment.
Such companies have traditionally focused on earlier stages of chipmaking, when circuitry is built onto
