RISC-V Foundation Showcases Continued Momentum and Growth at Embedded World 2019

RISC-V Foundation:

WHERE: Hall 3A, Booth No. 3A-536, N¼rnbergMesse, Messezentrum 1, 90471 N¼rnberg, Germany

WHEN: Tuesday, Feb. 26 “ Thursday, Feb. 28, 2019

WHAT: At Embedded World 2019, the RISC-V Foundation will be exhibiting at Hall 3A, Booth No. 3A-536, and will feature live demonstrations from co-exhibiting RISC-V Foundation member companies Andes Technology, CloudBEAR, GreenWaves Technologies, Imperas Software, SiFive, Syntacore and UltraSoC. Throughout the show, the booth will feature talks from RISC-V Foundation member companies. The RISC-V Foundation is also hosting a scavenger hunt across the show floor, challenging attendees to visit different booths in the RISC-V ecosystem for the chance to win a prize.


Subscribe to the Global Banking & Finance Review Newsletter for FREE
Get Access to Exclusive Reports to Save Time & Money

By using this form you agree with the storage and handling of your data by this website. We Will Not Spam, Rent, or Sell Your Information.
All emails include an unsubscribe link. You may opt-out at any time. See our privacy policy.

The main conference program will also feature a variety of RISC-V sessions, including a full day of RISC-V talks on Feb. 26 and a half-day RISC-V Workshop on Feb. 27, chaired by Cesare Garlati at the prpl Foundation and Hex Five Security. Speaking sessions include:

Session 5.1: RISC-V I Overview (Feb. 26)

  • RISC-V; Practical Industry Approach to Getting Started with This Technology
    • When: 9:30 “ 10 CET
    • Who: Robert Oshana, NXP Semiconductors
  • How to Benefit from RISC-V Based Linux for Embedded Industrial Applications
    • When: 10:00 “ 10:30 CET
    • Who: Krishnakumar R, Microchip Technology
  • The Soul of a New SoC: Hands-on Experience with Embedding a RISC-V Core
    • When: 10:30 “ 11 CET
    • Who: Onno Martens, Trinamic Motion Control Gmbh & Co. KG
  • Methodology for Implementation of Custom Instructions in the RISC-V Architecture
    • When: 11:30 “ Noon CET
    • Who: Larry Lapides, Imperas Software
  • Compliance Methodology and Initial Results for RISC-V ISA Implementations
    • When: Noon “ 12:30 CET
    • Who: Lee Moore, Imperas Software

Session 5.2: RISC-V II Security (Feb. 26)

  • Maintaining Security in a Heterogeneous and Changing World
    • When: 14:30 “ 15:00 CET
    • Who: Jon Geater, Jitsuin; Cesare Garlati, prpl Foundation and Hex Five Security
  • A New Zero-Trust Model for Securing Embedded Systems
    • When: 15:00 “ 15:30 CET
    • Who: Chris Conlon, wolfSSL; Cesare Garlati, prpl Foundation and Hex Five Security

Session 5.3: RISC-V III System (Feb. 26)

  • User Mode Interrupts: a Must for Securing Embedded Systems
    • When: 16:00 “ 16:30 CET
    • Who: Prof. Sandro Pinto, Universidade do Minho; Cesare Garlati, prpl Foundation and Hex Five Security
  • Embracing a System Level Approach: Combining Arm & RISC-V in Heterogeneous Designs
    • When: 16:30 “ 17:00 CET
    • Who: Gajinder Panesar, UltraSoC
  • RISC-V: High Performance Embedded SweRV Core Microarchitecture, Performance and Implementation Challenges
    • When: 17:00 “ 17:30 CET
    • Who: Dr. Zvonimir Bandic, Western Digital

Class 5.2: RISC-V Workshop (Feb. 27)

  • How to Build a RISC-V Embedded System In Just 30 Minutes
    • When: 9:30 “ 10:30 CET
    • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Drew Barbier, SiFive
  • How to Secure a RISC-V Embedded System In Just 30 Minutes
    • When: 10:30 “ Noon CET
    • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Don Barnetson, Hex Five Security
  • Trusted Execution Environments: A System Design Perspective
    • When: Noon “ 12:30 CET
    • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Boran Car, Hex Five Security

Session 6.3: Software Engineering II Design & Modeling (Feb. 27)

  • Design Cycle Acceleration for Hardware/Software Co-Design with Renode
    • When: Noon “ 12:30 CET
    • Who: Steve Milburn, Dover Microsystems and Michael Gielda, Antmicro

Expert Panel (Feb. 27)

  • Opportunities and Risks in Open Source Processors
    • When: Noon “ 13:00 CET
    • Who: Cesare Garlati, prpl Foundation and Hex Five Security; Markus Levy, NXP Semiconductors; Ted Marena, Western Digital; Tim Whitfield, Arm

Read more about RISC-V activities at Embedded World here: https://riscv.org/2019/02/embedded-world-2019.

To learn more about the RISC-V Foundation, its open, free architecture and membership information, please visit: www.risc-v.org. To schedule a meeting at Embedded World, please email [email protected].

About RISC-V Foundation

RISC-V (pronounced risk-five) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 200 member organizations building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.The RISC-V Foundation, a non-pinnovation. Theion controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1
(415) 694-6700
[email protected]