RISC-V Foundation Announces Free Getting Started with RISC-V Events in Five Cities in China

RISC-V Foundation:

WHAT: The RISC-V Foundation will be hosting a series of free, one-day Getting Started with RISC-V events in China.

WHEN & WHERE:

  • Shenzhen: May 6 at the Crowne Plaza Landmark Shenzhen
  • Chengdu: May 8 at the Sheraton Chengdu Lido Hotel
  • Shanghai: May 13 at the Hyatt on the Bund
  • Hangzhou: May 14 at the Alibaba Group Corporate Campus
  • Beijing: May 16 at the Crowne Plaza Zhongguancun, Beijing

DETAILS: The RISC-V Foundation, in collaboration with the Linux Foundation, is hosting a series of free, one-day Getting Started with RISC-V events to showcase innovative RISC-V implementations from members of the RISC-V Foundation. Participating companies include RISC-V Foundation members Alibaba Group, Andes Technology, Codasip, GreenWaves Technologies, Nervos, Nuclei System, NXP, PerfXLab, SiFive, Syntacore, Tangram, UC TECH IP and UltraSoC.

Please visit the page for each event to learn more:

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For press interested in attending and scheduling meetings with the RISC-V Foundation and member companies, please email: [email protected].

To learn more about the RISC-V Foundation, the free and open RISC-V architecture and membership information, please visit: https://riscv.org.

About RISC-V Foundation

RISC-V (pronounced risk-five) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. Founded in 2015, the RISC-V Foundation comprises more than 235 members building the first open, collaborative community of software and hardware innovators powering a new era of processor innovation. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem.

Allison DeLeo
Racepoint Global for RISC-V Foundation
Phone: +1
(415) 694-6700
Email: [email protected]